1. Field of the Invention
The present invention relates to a method of designing a semiconductor device and, in particular, to a method of assigning power supply voltage of a semiconductor device in which plural types of clocks are applied to a logic region.
2. Description of the Background Art
Referring to FIG. 19, a conventional method of assigning power supply voltage will be described. In the configuration of FIG. 19, a logic region on a semiconductor substrate is divided into two regions of domains D1 and D2, and clocks CK1 and CK2 having different frequencies are provided to the domains D1 and D2, respectively.
From a data output of a flip flop that operates using a rise edge of clock as a trigger, data is applied to logic gates to be formed in the domains D1 and D2, and the data is then transferred in the sequence in which the logic gates are connected.
In the domains D1 and D2,the power supply for operation is provided from a power supply source that is called “power supply bump.” FIG. 19 shows the state that a plurality of power supply bumps BP are disposed in a matrix in the domains D1 and D2, respectively.
An individual power supply bump BP is connected to a metal power supply line WL1 that extends linearly across the domains D1 and D2. A plurality of power supply lines WL1 are disposed in parallel. A plurality of power supply bumps BP are directly connected to a single power supply line WL1. The same power supply voltage is applied from the exterior to these power supply bumps BP. For instance, a power supply voltage V is applied (assigned) to the uppermost power supply line WL1 in FIG. 19, and a power supply voltage G is applied (assigned) to the next lower power supply line WL1, thus repeating the sequence of assignment. For instance, a drain power supply voltage VDD and a source power supply voltage VSS in a MOS transistor are applied as power supply voltages V and G, respectively.
In the layer underlying the power supply lines WL1, a plurality of power supply lines WL2, which are orthogonal to the power supply lines WL1 when viewed from above, are disposed in parallel. An interlayer insulating film electrically insulates the power supply lines WL1 and WL2. In portions at which both of the power supply lines cross when viewed from above, a via hole is formed by etching etc., such that it penetrates through the interlayer insulating film. The power supply lines WL1 and WL2 are electrically connected to each other by via contacts VH that are obtained by filling the via hole with a conductive material. Therefore, the voltage of the power supply line WL1 is to be applied (assigned) to the power supply line WL2 that is electrically connected to the power supply line WL1 through the via contacts VH.
A ground voltage (0 V) is applied to a half of the plural power supply lines WL1 and WL2. That is, no voltage is substantially applied thereto, however, such lines are also referred to as a “power supply line.”
The leftmost power supply line WL2, as viewed in FIG. 19, is electrically connected to the power supply line WL1 applying a power supply voltage V, so that the voltage V is applied to the line WL2. The second power supply line WL2 from the left is electrically connected to the power supply line WL1 applying a power supply voltage G, so that the voltage G is applied to the line WL2. Thus, the sequence of electrical connection is repeated.
The power supply lines WL2 to which a power supply voltage V is applied, and the power supply lines WL2 to which a power supply voltage G is applied, are electrically connected to the power supply lines of the lowermost layer that provide power source to a gate array constructed on the semiconductor substrate. The power supply voltages V and G are applied from the power supply lines WL2 to the source/drain layer of the gate array.
Thus, in the conventional method of assigning power supply voltage, the power supply lines WL1 to which a power supply voltage V or G is applied are disposed so as to extend across the domains D1 and D2 to which the clocks CK1 and CK2 having different frequencies are provided. Thereby, the voltage V and G are also applied to the domains D1 and D2, respectively.
The problem is power supply noise caused by a frequency difference between the clocks CK1 and CK2. As stated above, from the data output of the flip flop that operates using the rise edge of clock as a trigger, data is provided to logic gates to be formed in the domains D1 and D2. There are a large number of combinations of such logic gate and flip flop in the domains D1 and D2.
Since many of the plural flip flops operate in synchronization with each other, the maximum power is consumed at the timing of clock rises. At that time, current flows on the power supply lines WL1, WL2, and power supply bumps BP, which current causes variations in power supply voltage value. This is power supply noise.
The relationship between the timing of the clocks CK1 and CK2, as well as the power supply noise will be described with reference to FIG. 20, showing a timing chart of the clocks CK1, CK2, and variations in power supply voltages VDD and VSS.
As shown in FIG. 20, the clocks CK1 and CK2 differ from one another in frequency, and their clock rise edges are basically asynchronous. Accordingly, the temporal variations of power supply voltage VDD occur in response to the pulse rise and fall of the clocks CK1 and CK2. The variations of power supply voltage VDD is power supply noise NZ. Needless to say, a similar noise occurs in power supply voltage VSS.
Unless the timing of occurrence of power supply noise NZ is synchronous, the interaction of power supply noises will occur. This increases the influence on the operation rate of the logic gates than if a single clock is applied.
In the foregoing, it is described that the clock rise edges are basically asynchronous when the clocks CK1 and CK2 have different frequencies. However, if the clocks CK1 and CK2 are of multiple frequencies, their rise edges will coincide somewhere.
Referring to FIG. 20, the rise edge of the initial pulse of the clock CK1 is synchronized with that of the clock CK2. At this time, a plurality of flip flops operate simultaneously in both of the domains D1 and D2,and a peak value of power supply noise NZ is increased than if the flip flops operate in each domain. In FIG. 20, there is shown in such a way that the power supply noise NZ oscillates. This is because the inductance accompanied by the power supply line of a clock driver produces the counter electromotive force in an opposed direction relative to the power supply variations generated at the time of switching.
Such an increase in power supply noise NZ may have an effect on clock signals. That is, the clocks CK1 and CK2 are amplified by the clock drivers disposed in the domains D1 and D2,respectively, and are then provided to the flip flops. Each clock driver is configured with an inverter driven by the power supply voltage VDD or VSS. Therefore, if the power supply voltages VDD and VSS vary, the pulse rise and fall edges of the clocks CK1 and CK2 vary temporally to cause clock jitter CJ, as shown by broken lines in FIG. 20. The magnitude of the clock jitter CJ corresponds to the magnitude of power supply noise NZ, and the clock jitter CJ increases when the rise edge of the clock CK1 is synchronous with that of the clock CK2.
Clock jitter contributes to a mismatch of the timing of clock edge in a plurality of flip flops constituting a single data path, thereby affecting the timing of data transfer. Specifically, a clock skew caused by layout is present in the clocks provided to the flip flops constituting the data path. The clock skew, combined with the clock jitter, increases or decreases the cycle time between flip flops, resulting in a mismatch of the timing of clock edges.
Such an increase or decrease of the cycle time between flip flops reduces the margins of set up time and hold time of the flip flops on the data path, and therefore causes to lower the logic highest operating frequency.
The control of clock skew is increasingly more difficult with miniaturization of transistors and with increasing logic scale. Further, when an asynchronous data transfer within the chip is required, inevitable result is that clocks having different phases and frequencies are present in a logic region.
In these circumstances, it is essential to control the generation of clock jitter. As discussed above, the power supply noise that causes clock jitter results from the fact that different domains to which different clocks (in phase and frequency) are applied operate with the power source of the same line.
Therefore, in order to eliminate the influence of power supply noise caused by different clocks, power supply voltages may be applied individually to each of the different domains to which different clocks are applied.
The conventional method of assigning power supply voltage described with reference to FIG. 19, however, complies with assignment of a single power supply voltage, thus failing to individually apply power supply voltages to different domains.